Nanoelectronic devices and circuits

ABSTRACT

Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines ( 8, 16, 18 ) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels ( 20 ) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to μA) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.

The present invention relates to nanoelectronic diode devices andcircuits.

Known techniques for making integrated circuits of micrometer dimensionscommonly involve multiple steps comprising overlying and aligningdifferent shapes and patterns in e.g. photolithographic techniques, withdiffusion and implantation steps. However these techniques are difficultto apply for manufacturing extremely small circuits of nanometricdimensions. With current advances in technology, complementarymetal-oxide semiconductor (CMOS) field-effect transistors inmicroprocessors have a gate length already close to 100 nm. In order tocontinue the miniaturisation of the semiconductor devices, the industryfaces great fabrication, technical and economic challenges. Futureintegrated circuits must be built with devices of nanometric dimensionsbased on new concepts.

Techniques for generating circuit features of nanometric dimensions on asubstrate include X-ray beam and electron beam lithography. Oneparticular technique is disclosed in U.S. Pat. No. 5,772,905, the socalled nano imprint process, in which a mould having extremely smallprojections formed by E-beam lithography is pressed into a plasticspolymer layer on a substrate so as to create depressions in the layercorresponding to the mould projections. An etching process may then becarried out to expose the substrate in the depression areas, andsubsequent etching or deposition processes may be carried out to definefeatures of an integrated circuit. However, U.S. Pat. No. 5,772,905 doesnot disclose a complete integrated circuit, nor a method of implementinga complete circuit.

EP-A-0464834 discloses a transistor formed in a AlGaAs/GaAsheterostructure by means of a geometric pattern of insulative trenches.A 600 m wide one-dimensional channel is insulated laterally from 2DESareas, which provide transistor gates, by 700 nm wide deep mesa etchedtrenches. The conductivity in the ID channel has a strict lineardependence on the applied gate voltage across the channel.

SUMMARY OF THE INVENTION

In accordance with at least a preferred form of the invention, we havediscovered that positioning two insulative features close to one anothersuch as to define a narrow elongate channel having a width dimension ofthe order of nanometres, provides a circuit component, wherein thecurrent flow through the channel is a function of voltage applied acrossthe length of channel, in a predetermined manner. In a preferredembodiment, the circuit component comprises a diode, but it may forexample comprise a transistor or resistor.

The invention provides an electronic circuit component comprising asubstrate supporting mobile charge carriers, insulative features formedon the substrate surface to define first and second substrate areas oneither side of the insulative features, the insulative featuresincluding first and second regions which are positioned close to oneanother but spaced apart so as to provide an elongate channel whichprovides a charge carrier flow path in the substrate from the first areato the second area; and

wherein said elongate channel is dimensioned and arranged such that theparameters of the charge carrier flow path are dependent on a potentialdifference between said first and second areas.

For the purposes of this specification, “circuit component” means a partor element of an integrated circuit which provides a desired circuitfunction such as a transistor, capacitor, diode or logic gate.

Where the circuit component is a non-linear device such as a diode, itis necessary to break the inversion symmetry in the charge carrier flowpath. Thus the insulative regions are such that the applied voltageoperates in a different way, dependent on its polarity, to open or closethe channel, as described in more detail below. This provides highlyasymmetric current-voltage characteristics, similar to or better thanthat of normal diodes.

For the purposes of the present specification, “insulative” is to beunderstood as a relative value, as compared to the conductivity of thesubstrate. In one embodiment, trenches forming insulative barriers maybe weakly conductive, forming very narrow conductive channels. In somecases it is preferable to have a little conduction when no voltage isapplied, which may provide very sensitive detection or mixing of veryweak signals, even though a little leakage current exists.

In one preferred embodiment, the insulative features are formed astrenches or lines dividing the substrate into first and second areas.Further trenches or lines extending at an angle to the dividing linesdefine the channel, extending into one of the first and second areas.Electrical voltages may be applied to the first and second areas bymeans of appropriate electrical contacts and a voltage difference iscreated across the insulative dividing lines. The outer sides of thechannel defining lines are exposed to its voltage in the one area. Whenthe electrical voltage across the channel is sufficiently high, theelectric field creates a depletion region in which no charge carriersexist. Provided the channel is sufficiently narrow and sufficientlylong, a perfect closing or pinch off of the gap is achieved so that no,or at any rate very little, current flow is possible. Thus adiode-action is created. When the applied voltage is in the forwarddirection, the applied voltage will electrostatically widen the channelin addition to making the channel potential lower, which allows thecarriers to flow easily in the forward direction.

The width of the channel is preferably of the order of 30 nanometres.The maximum width of channel is generally 100 nm, whereas the narrowestwidth of channel can extend down to close to zero. If for example anovergrowth is provided after etching of the grooves, the depletionaround the etched lines is much less, and the designed channel width canbe much less. The length of the channel is also determinative of theoperation of the device and in order to achieve diode action, the lengthmust be at least of the order of 100 nm for a substrate material ofInGaAs/InP, while the maximum length may be a few microns or more. Thelengths depend to a large extent on the material of the substrate andthe purpose intended for the circuit component. Thus the presentinvention can provide a perfect diode action with a very simpleconstruction. Since there are no P-N junctions creating minoritycarriers, the electrical characteristics of diode are very clean so thatno reverse current is provided on pinch off.

In a modification, one side of the channel may be exposed to a furthercontrol or modulating voltage existing in a closed area of thesubstrate. This modulates current flow through the channel, and thuscreates a transistor device.

The substrate may provide a two-dimensional electron gas; alternativelyit may have any other desired characteristic. Any desired substratematerial may be used, for example silicon or bulk SiGe material. Ascurrently available, InGaAs/InP material is used.

Although primarily serving for electronic purposes, the devices of theinvention may also be used as optical components. For example where adiode device is constructed from two insulative barriers defining anarrow elongate channel, in the condition where the channel is eitheralmost pinched off or nearly closed, it is very sensitive to lightillumination i.e. the depletion around the insulative barriers can bevery much reduced. As a result even a weak light will dramaticallyincrease the current at a certain bias by orders of magnitude. This canbe directly used as a light detector or optical switch.

The diode according to the invention may alternatively be employed as aphotodiode, light being generated by the avalanche effect, whereelectrons are generated from the valence band and leave behind a hole.Generated holes recombine with electrons and generate light.

In another embodiment, the electrical and optical parameters of thechannel of the device may be made very sensitive to a small number of,even a single one, molecules of a certain type adsorbed onto the surfaceof the device—thus the device may be used as a sensor for suchmolecules.

In accordance with the invention, it is possible to make integratedcircuits of nanometric dimensions in essentially a single fabricationstep or at any rate a very small number of processing steps, all ofwhich follow a single pattern of features. Any suitable method forproducing etched features may be employed, including e-beam lithographyand the nano-imprint method referred to above. This is greatlysimplified as compared with prior art processes of making integratedcircuits, involving multiple steps comprising various steps involvingoverlying and aligning different shapes and patterns. Nevertheless, thepresent invention may incorporate a subsequent step of forming a widearea gate covering multiple circuit components, without disturbing theessential simplicity of the process.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described by way ofexample with reference to the accompanying drawings wherein;

FIGS. 1A–1E show schematic views, together with a scanning electronmicrograph, of a first embodiment of the invention comprising a diode;

FIGS. 2–6 are graphs of experimental current-voltage characteristics ofthe diode-type devices shown in FIG. 1, but with characteristics alteredto give different operating characteristics;

FIG. 7 is schematic views of modified forms of the diode of FIG. 1;

FIGS. 8A–8B show a further preferred embodiment of the inventioncomprising a bridge rectifier;

FIGS. 9A–9C show a further preferred embodiment of the inventioncomprising an OR gate;

FIGS. 10A–10C show a further preferred embodiment of the inventioncomprising an AND gate;

FIGS. 11A–11B shows a further preferred embodiment of the inventioncomprising a diode-type device with a tuneable threshold, which can alsofunction as a transistor-type device;

FIG. 12 shows a negative differential resistance (NDR) characteristic ofa preferred embodiment of the invention;

FIG. 13 is a schematic circuit diagram of a GHz oscillator employing thedevice of FIG. 12;

FIGS. 14 and 15 are schematic views of the embodiment of FIG. 16incorporated into scanning matrices; and

FIG. 16 is a schematic view of a further embodiment of the invention,comprising a photodiode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The roadmap of micro-electronics has long indicated that we will verysoon reach the limits of conventional semiconductor devices, and nearfuture integrated circuits must be built with nanodevices based on newconcepts. Furthermore, it is highly desirable that these new nanodevicescan be made on standard silicon wafers. Despite great efforts in makingnanodevices working at room temperature, there is very little success.The reason is that most nanodevices proposed so far require a featuresize of about a few nm.

The invention includes diode-type devices. The current-voltagecharacteristic of the diode-like devices is just like that of aconventional diode, but both the threshold voltage (from 0V to a fewvolts) and the current level (from nA to μA) can be tuned by orders ofmagnitude by simply changing the device geometry, with no need to changethe property of the host material by doping, diffusion, etc. Better thana pn diode, the leakage current under the backward biased condition canbe negligibly low. Three-terminal devices can provide both thefunctionality of a transistor and that of a diode, meaning greatflexibility in construction of circuits. When used as a three-terminaldevice in a modified design, the device can exhibit both thefunctionality of a transistor and that of a diode, meaning greatflexibility in construction of circuits.

Although currently implemented on InGaAs/InP material, the devices canbe reliably and reproducibly made on standard silicon wafers, since theworking principle does not rely on a high electron-mobility. As will beshown below, a full family of logic gates, such as OR, AND, and NOT, canbe constructed only by simply etching grooves in the substrate.Therefore, the invention will considerably simplify the manufacture ofdiode-type devices as well as integrated circuits, and hence greatlyreduce the production cost.

Referring now to FIG. 1, FIGS. 1A and 1E show a scanning electronmicroscope (SEM) image of a diode-type device. Electrical contacts 4, 6are formed on left and right sides of the InGaAs/InP substrate 2 and acentral insulative line 8 (here etched trenches) divides the substrateinto left and right areas 10, 12. The width of the etched trenches areabout 100 nm. To fabricate the device, we first spin a layer ofelectron-beam resist (ZEP-520) on the InGaAs/InP substrate, whichcontains a conductive (mobile electrons) layer about 50 nm below thesurface. The designed pattern was then defined using electron-beamlithography. After development of the resist after the electron-beamexposure, wet chemical etching was used to make the trenches of about100 nm deep, i.e. etching through the conductive layer and forminginsulative lines.

In the centre of line 8, two line regions 16, 18 are formed extendingfrom line 8 onto substrate area 12. Lines 16, 18 are perpendicular tothe length of line 8 and having a length of about 500 nanometres. Thus,the etched trenches not only define a narrow channel but, extending onlyinto area 12, also break the inversion symmetry along the channelcurrent direction. The elongate channel 20 has a width of about 50nanometres, which provides an electron flow path for mobile electrons inthe substrate to travel from the left side 10 to the right side 12 ofthe substrate, or in the opposite direction.

In a condition where no voltage is applied to terminals 4 and 6, therewill exist in channel 20 depletion regions 22 as shown in FIG. 1Badjacent each line region 16, 18 so that only a narrow area of the flowpath is available for electron conduction. These depletion regions arecreated by reason of surface states and the Fermi level at the etchedsurface. The depletion regions are shown as indicating their effect ontransport of electrons through the channel. As shown in FIG. 1C when apositive voltage is applied to terminal 6 and a negative voltage appliedto terminal 4, a positive voltage exists on the outer sides of lineregions 16, 18, and this acts to decrease the size of the depletionregions 22 by electrostatically lowering the potential in the channel.In this condition, the electron conduction and therefore the currentwill be large.

In FIG. 1D, when the voltage polarities are reversed so that a positivevoltage is applied-to terminal 4 and a negative voltage to terminal 6,the negative voltage existing on the outer sides of line regions 16, 18electrostatically lifts the potential in the channel. This createseither a much narrower channel or even a wholly pinched off channel. Inthe latter case, carriers cannot penetrate from one side to the otherconsidering the large length of channel. Thus, only little or even nocurrent will flow through the channel, in contrast to the oppositevoltage polarity, meaning that a diode-like functionality is created asshown in FIG. 1E.

Furthermore, the amount of minority carriers will be negligible as noP-N junctions are created. Therefore, the leakage current underreverse-biased condition can be extremely small and was observedexperimentally to be down to below pA.

FIGS. 2–6 are graphs of experimental current-voltage characteristics ofthe diode-type devices shown in FIG. 1, but with characteristics alteredto give different operating characteristics. FIG. 2 shows thecharacteristic for a device similar to FIG. 1 (but with a channel lengthof 700 nm and width of 40 nm). It can be seen that for a voltage above0.9 volts created between terminals 4, 6, the current through channel 20increases extremely rapidly so that at a voltage of 2 volts, there is acurrent of about 6 micro amps. Below the value of 0.9 volts, no currentis observed. The characteristics are given for a temperature of 4.2°Kelvin.

In FIG. 3, the dimensions of the elongate channel 20 are adjusted(channel length 1000 nm and width of 50 nm) so that the thresholdvoltage is well below 0.02 volts, i.e. very close to 0.

In FIG. 4, a device is shown with dimensions of the elongate channel ofFIG. 3. The characteristic shown is at room temperature. A less thanperfect characteristic is given with a little current under thereverse-biased condition, which can be reduced to zero by optimisationssuch as slightly reducing the channel width As shown below in FIGS. 10Band 10C, this less than perfect characteristic can be desirable in somelogic circuits.

Referring to FIG. 5, the dimensions of the channel are adjusted (width20 nm, length 700 nm) so that there is a large positive thresholdvoltage of about 2 volts. This characteristic is measured at roomtemperature.

In FIG. 6, a characteristic of a device with channel dimensions of FIG.3 is measured at a temperature of 240° Kelvin. The threshold is exactly0 volts and there is no current under the reverse-biased condition. Thecharacteristic is close to an ideal diode, with no noticeable leakagecurrent and zero threshold voltage.

Referring now to FIG. 7, this shows variations in geometricalconfiguration of line regions 16, 18 defining elongate channel 20. InFIG. 7A the lines 16, 18 inwardly taper from lines 8 so that width ofthe channel 20 is at a minimum at the free ends of lines 16, 18. Thishas advantages in better control over current flow.

In FIG. 7B, the line regions 16, 18 taper in the opposite direction sothat the width of the elongate channel 20 is at a minimum adjacent line8 and at a maximum at the free ends of lines 16, 18.

In FIG. 7C the line regions 16, 18 are castellated so that the width ofthe channel 20 varies between a small value a where lines 16, 18 areclose to one another, and a large value b in the areas where lineregions 16, 18 are far from one another. This construction may createnon-linear quantum transport effects.

In FIG. 7D, the line regions 16, 18 outwardly curve from lines 8relative to one another until they reach a maximum value apart m, whencethe lines curve back inwardly to a width d equal to the width d atregions 8. This construction may create non-linear quantum transporteffects. In all of FIG. 7, the width of the channel does notsignificantly exceed 100 nm.

Referring now to FIGS. 8A to 8B, a second embodiment of the inventioncomprises a bridge rectifier, shown schematically in FIG. 8A wherein analternating voltage is applied across terminals 40, 42 and a unipolarrectified voltage is derived at terminals 44, 46.

One implementation of this bridge rectifier is shown in FIG. 8B whereina InGaAs/InP substrate is divided into essentially four areas 50, 52,54, 56. These areas are separated by insulative lines, with line 60having elongate channels 62, 64 defined by line regions 66, 68interconnecting region 50 with regions 52 and 54. An insulative line 70wholly separates region 52 from region 54. An insulative line 80 hasline regions 82, 84 which define elongate channels 86, 88 which permitcurrent flow between region 56 and regions 52, 54. Terminals 40, 42 arerespectively connected to regions 52, 54 so that an alternating voltageexists in these regions. Terminal 46 is connected to region 50 andterminal 44 is connected to region 56.

Thus in operation with a positive phase applied to terminal 40 and anegative phase to terminal 42, current flow is encouraged throughchannel 62, but inhibited through channel 64. Channel 86 will bedepleted since the voltage in region 56 will be negative relative to thepositive voltage existing in region 52. Channel 84 however will howeverbe opened since the voltage within region 56 will be positive relativeto the large negative voltage existing in region 54. Thus current flowwill be enabled through channel 62 from region 52 to region 60,resulting in a positive voltage at terminal 46. Current flow willenabled through channel 84 from region 56 to region 54, resulting in anegative voltage at terminal 44.

When the polarities at terminals 40, 42 are reversed, and a negativevoltage is applied to region 52, together with a positive voltageapplied to region 54, then in a similar manner to the above, channel 64will be open to provide current flow between region 54 and region 50 tocreate a positive voltage at terminal 46. Channel 86 will be opened toenable current flow between region 52 and region 56, to create anegative voltage at terminal 44. Thus a full wave rectification actionis provided.

Thus channel 62 defined by the insulative lines corresponds to the upperleft diode in FIG. 8A. Similarly, channel 86 corresponds to the upperright diode, channel 64 corresponds to the lower left diode, and channel84 corresponds to the lower right diode in FIG. 8A. Thus, solely byfabrication of insulative lines, the bridge rectifier circuit isconstructed. This shows that the invention substantially simplifies thedesign and manufacture of both devices and circuits, and hence greatlyreduce the production cost.

Referring now to FIG. 9, an OR gate is constructed solely by fabricationof insulative lines on a conductive circuit. FIG. 9B shows an equivalentcircuit. In FIG. 9C, an OR gate facility is provided by dividing asubstrate into three areas, 100, 102, 104, each with a respectiveterminal 106, 108, 110. The substrate regions are created by insulativelines 112, 114, and elongate flow path channels 116, 118 are createdbetween regions 100 and 102 and 104 and 102 by insulative line regions120, 122.

In operation when a positive voltage is applied to either of terminals106 and 110, the respective flow channel 116, 118 will be openedenabling current flow and for the positive voltage to be transmitted tothe output terminal 108. In the situation where negative voltages areapplied to both of terminals 106, 110, neither voltage will betransmitted through channels 116, 118 and therefore the output voltageat terminal 108 will remain low. It is clear that channel 116 in FIG. 9Ccorresponds to the upper diode in FIG. 9B, while the channel 118corresponds to the other diode. In operation when a positive voltage isapplied to either of terminals 106 and 110, the respective channel 116,118 will be opened enabling current flow and for the positive voltage tobe transmitted to the output terminal 108. In the situation where alogic LOW voltage is applied to both of terminals 106, 110, the outputat terminal 108 will remain low.

Referring now to FIG. 10A, an AND gate facility is provided. FIG. 10Bshows an equivalent circuit. In FIG. 10C, an AND gate facility isprovided by dividing a substrate into four areas, 152–158, each with arespective terminal 162–168. The substrate regions are created byinsulative lines 170–176, and elongate flow path channels 180–184 arecreated, which define diodes. Note that channel 180 is slightly widerthan channels 182 and 184 such that channel 180 provides acharacteristic like that in FIG. 4 with a certain conductance at a lowbias voltage while channels 182 and 184 provide a characteristic likethat in FIG. 5 and, for the best, provide an “ideal” characteristic asin FIG. 6. In operation, a positive rail voltage is applied to terminal162. When logic HIGH voltages are applied both to terminals 164, 166,the diodes 182, 184 are reverse-biased, and the positive rail voltage istransmitted through channel 180 to output terminal 168. When either ofinput terminals 164, 166 has a logic LOW voltage applied, the respectivediode becomes forward-biased and has only a little voltage drop over itsince the diode 180 is reverse-biased and has a very large resistance.As a result, the voltage at the output terminal will be a logic LOWsignal. Thus an AND function is provided. This circuit may employ NDR,as described below with reference to FIG. 12B for reaching zero current.

Referring now to FIG. 11A, a three-terminal transistor device is shown.The design is based on the design of FIG. 1B, and similar paths areindicated by the same reference numeral.

An insulative line 8 divides the substrate into a left area 10 and aright area 12, which have respective electric contacts 200, 202.Insulative lines 16, 18 extending perpendicularly to line 8 define anarrow channel 206 extending between areas 10 and 12. In addition afurther insulative line 212 extends from the free end of line 16parallel to line 8 in order to define a further substrate area 14. Thisarea has a further electrical contact 204. Thus an extra insulative line212 defines a side gate region 204. The side gate terminal 204 issimilar to the gate of a conventional field-effect transistor (FET). Ata given voltage applied to the side gate, measurement between terminals200 and 202 still shows a diode-like characteristic. However, by varyingthe voltage on the side gate, the threshold voltage of the diode(between terminals 200 and 202) is tuned. Therefore, the device can beregarded as a diode with a tuneable threshold, which can be representedby the symbol in FIG. 1B.

Since the conductance and hence the current of the channel 206 can begreatly tuned by applying a voltage on the side gate, the device alsohas the functionality of a field effect transistor. This enables thedesign of, for example, a whole family of logic gates including NOT,NAND, NOR, XOR gates, etc., with high efficient and low powerconsumption. A NOT or inversion capability is provided by inversion ofvoltage at 204 at the output terminal. The combination of a diodeelement and transistor element provides buffer elements for logiccircuits, and enables cascading for larger circuits. The devices andgates are NMOS in nature, as opposed to CMOS which is currently used:hence low power consumption.

Referring to FIG. 12, there is shown that for certain dimensions ofchannel (here length 1 micron, width 50 nm), a pronounced negativedifferential resistance (NDR) characteristic is exhibited under thereverse-biased condition at room temperature. In other words, in acertain voltage range an increasing of applied voltage results in areduced current. NDR devices are widely used as the central elements inhigh-speed electronic oscillators. The speed of oscillation may be 100'sof GHz, even THz.

An oscillator circuit based on a NDR device is shown in FIG. 13. A diode130, of the form shown in FIG. 1, is connected in parallel with acapacitor 132 and inductor 134. A voltage source 136 provides power.Oscillatory signals are generated across load 138 and the diode. In thecase when the oscillator operates at very high frequencies, thegenerated microwave can be radiated directly from the surface of thedevice. This is useful in VHF, UHF as well as in GHz regimes, and onesuch example is as a 40 GHz switch for photonics applications.

Referring to FIG. 16, a photodiode 160 forming a further embodiment ofthe invention is shown schematically, similar parts to these of FIG. 1being denoted by the same reference numeral. The photodiode employs theavalanche effect, which occurs in a reverse-biased condition and whereelectrons are generated from the valence band and leave behind holes.Generated holes recombine with electrons and generate light. Theavalanche effect normally occurs when electric field is very localised,and the diode produces a very localised field along the channeldirection at one end of the channel. The intensity of the field inregion 162 is sufficiently great that electrons leaving the valence bandcollide with other electrons, forcing these electrons also to leave thevalence band; holes undergo a similar process; hence the avalancheeffect.

FIG. 14 is a schematic view of a rectangular matrix of elements, eachelement comprising a photodiode 160 as shown in FIG. 16. The photodiodesare addressed by row address lines 144 and column address lines 146.This provides a randomly accessed light-emitting source array with theadvantages of easy and cheap fabrication as well as easy integration,very large arrays are practical. Whilst a drawback is the possible lowefficiency of light generation, in those cases when this is not a bigproblem whereas production cost or integration density are the mainissues, this is a practical option. The advantage of FIG. 14 is ease ofidentification of individual photodiodes, and individual row and columnaddress lines.

FIG. 15 represents a more practical version of FIG. 14, where theelectrical connections of each photodiode 160 are integrated withaddress lines 144, 146. Thus each photodiode element has insulativetrenches 150 extending towards an associated column address line 146, toprovide electrical connection thereto via substrate region 152. Eachphotodiode element has insulative trenches 154 extending towards anassociated row address line 144, to provide electrical connectionthereto via substrate region 156.

In FIGS. 14 and 15, the address lines may be of metal or of asemiconductor material, the same material as the substrate 2 of eachdiode.

Since, as discussed above the individual devices are very sensitivelight because of the narrow channel and the dominant role of the surfaceon the side of the channel, such an array would also be useful for lightdetection with high spatial resolution. Also it can be used whenimmersing in a solution, to detect spatial distribution of e.g.molecular concentration.

Given the examples above, the devices and circuits of the invention havea number of obvious advantages from device, material, and circuit pointsof view.

Device Point of View

-   -   Compared with a conventional diode, the new device concept has a        number of obvious advantages, such as    -   Simple: making devices by just writing lines (or trenches) as        shown in FIG. 1 a,    -   Cheap: only one fabrication step needed, no multiple-mask        alignments, and therefore suitable for using, e.g., nano-imprint        technique,    -   Can be reproducibly made: The device feature size can be        designed to be larger than 30 or 50 nm, so it can be made        reproducibly and reliably.    -   Good device/feature size for next 10 to 20 years: The device        feature size is between 10 to 100 nm, and the device size from        about 50 to 1000 nm. Hence, it meets the requirements for the        next generation of logic ICs as predicted by “International        Technology Roadmap for Semiconductors”.

Material Point of View

-   -   Since the working principle does not require a high        electron-mobility, SSDs can be readily made on standard silicon        wafers, or other materials such as Ge, GaAs, InP, InAs.

Circuit Point of View

-   -   Making circuits in one step: The above shows some of the        examples where dark lines are e.g. etched trenches, including a)        bridge rectifier, where by applying an AC voltage to the upper        and lower terminals a DC voltage is generated between the left        and right terminals, b) logic OR, in which if any of the left        two input terminals is applied with a logic high voltage, the        output will have a logic high output. In both cases, devices as        well as circuits are made by just writing/etching lines in one        fabrication step, rather than making dopings or gatings, etc. in        multiple steps requiring precise alignments.    -   Complete logic family: Other logic elements such as AND and NOT        have been designed. Therefore, a new, complete family of logic        elements can be made. Based on these basic logic        building-blocks, one can in principle construct fully        functioning, Si-based, logic circuits like adders. Another        noticeable advantage is that the logic voltage level can be        easily tuned to meet that of, for example, the standard CMOS        circuits.    -   Extremely low heating and power consumption: The device uses a        nano-channel and hence has low current levels. Experimentally we        have tuned the current level down to much less than nA simply by        changing the channel width. It has been expected that in 2014, a        typical microprocessor will consist of 4×10⁹ logic elements.        Even with our current initial devices, the total power        consumption is less than 10 W, much lower than expected/required        183 W.

1. An electronic circuit component comprising a substrate supportingmobile charge carriers, insulative features formed on the substratesurface to define first and second substrate areas on either side of theinsulative features, the insulative features including first and secondregions which are positioned close to one another but spaced apart so asto provide an elongate channel extending between the first and secondsubstrate areas, which provides a charge carrier flow path in thesubstrate from the first area to the second area, and wherein saidelongate channel is of predetermined width such that when a voltagedifference is applied between said first and second substrate areas suchas to cause flow of said mobile charge carriers through said elongatechannel, the voltage existing in the second substrate area influences,via said insulative features, the size of depletion regions existingwithin said elongate channel, whereby the conductivity characteristicsof the channel are dependent on said voltage difference.
 2. A componentaccording to claim 1, wherein the circuit component comprises a diode.3. A component according to claim 1, wherein the length of the elongatechannel is at least about 100 nanometres.
 4. A component according toclaim 1, wherein the width of the elongate channel is less than 500 nm.5. A component according claim 1, wherein the insulative features aredefined by first insulative lines separating said first and secondsubstrate areas, and second insulative lines extending at an angle tothe first insulative lines and defining said elongate channel.
 6. Acomponent according to claim 1, wherein the elongate channel extendsinto only one of the first and second substrate areas so that said firstand second regions are exposed to a voltage existing in the one area. 7.A full wave rectifier circuit, wherein a substrate is divided byinsulative lines into at least four areas each having a respectiveelectrical terminal, and elongate channels are selectively provided insaid insulative lines between said four areas in order to create diodes,each diode being as claimed in claim 2, for providing a full waverectification action.
 8. An OR gate circuit, wherein a substrate isdivided into at least three regions by insulative lines, a first regionproviding a first input terminal, a second region providing a secondinput terminal, and a third region providing an output terminal; a firstelongate channel is provided between said first region and said thirdregion, a second elongate channel is provided between said second regionand said third region, each channel providing a diode according to claim2, whereby to enable current flow between the regions upon applicationof appropriate voltages to the input terminals, whereby to obtain at theoutput terminal an output voltage reflecting an OR characteristic.
 9. AnAND gate circuit, wherein a substrate is divided into at least first,second and third regions by insulative lines, a first region providing afirst input terminal, a second region providing a second input terminal,and a third region providing an output terminal; and a first elongatechannel is provided between the first region and the third region, and asecond elongate channel is provided between the second region and thethird region, each channel providing a diode according to claim 2;whereby to enable current flow between the regions upon application ofappropriate voltages to the first and second inputs, whereby to obtainat the output an output voltage reflecting an AND characteristic.
 10. Acircuit according to claim 9, including a fourth substrate regionserving as a voltage rail and connected to said third region by anelongate channel providing a component according to claim 1 and servingas a resistor.
 11. A component according to claim 1, wherein theelongate channel is such that a negative differential resistivecharacteristic is provided.
 12. An oscillator circuit, including one ormore reactors, and a component according to claim
 11. 13. A componentaccording to claim 2 formed as a photodiode, wherein the dimensions ofsaid channel are such as to create a region wherein avalanche breakdownoccurs upon application of voltage such as to generate light.
 14. Amatrix array for light emission, comprising row and column addresslines, wherein each element of the matrix is a photodiode according toclaim
 13. 15. A component according to claim 2, arranged such as togenerate a detectable current when exposed to light or to a molecularspecies in solution.
 16. A matrix array for light detection, comprisingrow and column address lines, wherein each element of the matrix is acomponent according to claim
 15. 17. A component according to claim 2,wherein the length of the elongate channel is at least about 100nanometres.
 18. A component according to claim 2, wherein the elongatechannel is such that a negative differential resistive characteristic isprovided.
 19. An oscillator circuit, including one or more reactors, anda component according to claim
 18. 20. A component according to claim 1,wherein the width of the elongate channel is less than 100 nm.
 21. Acomponent according to claim 1, wherein the width of the elongatechannel is about 30 to 50 nm.